Main memory controller with multiple media technologies for big data workloads

Abstract SRAM and DRAM memory technologies have been dominant in the implementations of subsystems. In recent years, mainly driven by huge demands big data applications, NVRAM technology has emerged as a denser technology, enabling design new hybrid DRAM/NVRAM hierarchies that combine multiple media to balance capacity, latency, cost, endurance. Two main approaches are being applied hierarchies: address space approach, which relies on programmer or operating system choose where each page should be stored; (only) NVM faster (e.g. commodity DRAM) is needed acts cache boost performance. This approach presents architectural challenges such organization metadata tags) selection proper for component. contrast existing approaches, this work proposes controller leverages novel eDRAM MRAM mitigate bus contention improve performance space. The devised solution two-level hierarchy controller: sector (x)RAM cache. cache, much denser, helps significantly reduce number accesses NVRAM. Experimental results show implementing with best performing approach. Moreover, eRAM able miss penalty up 50% 80%, overall 15% 23%.